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1/20 july 2002 M34C02 2 kbit serial i2c bus eeprom for dimm serial presence detect psdip8 (bn) 0.25 mm frame so8 (mn) 150 mil width tssop8 (ds) 3x3mm 2 body size (msop) 8 1 8 1 tssop8 (dw) 169 mil width n two wire i 2 c serial interface n 100 khz and 400 khz transfer rates n single supply voltage: C 2.5v to 5.5v up to 400 khz for M34C02-w C 2.2v to 5.5v up to 400 khz for M34C02-l C 1.8v to 5.5v up to 100 khz for M34C02-r n software data protection for lower 128 bytes n byte and page write (up to 16 bytes) n random and sequential read modes n self-timed programming cycle n automatic address incrementing n enhanced esd/latch-up protection n more than 1 million erase/write cycles n more than 40 year data retention description the M34C02 is a 2 kbit serial eeprom memory able to lock permanently the data in its first half (from location 00h to 7fh). this facility has been designed specifically for use in dram dimms (dual interline memory modules) with serial presence detect. all the information concerning the dram module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. this bottom half of the memory area can be write- protected using a specially designed software figure 1. logic diagram ai01931 3 e0-e2 sda v cc M34C02 wc scl v ss table 1. signal names e0, e1, e2 chip enable inputs sda serial data/address input/ output scl serial clock wc write control v cc supply voltage v ss ground
M34C02 2/20 write protection mechanism. by sending the device a specific sequence, the first 128 bytes of the memory become permanently write protected. care must be taken when using this sequence as its effect cannot be reversed. in addition, the device allows the entire memory area to be write protected, using the wc input (for example by tieing this input to v cc ). the M34C02 is a 2 kbit electrically erasable pro- grammable memory (eeprom), or ganized as 256x8 bits, fabricated with stmicroelectronics high endurance, advanced, cmos technology. this guarantees an endurance typically well above one million erase/write cycles, with a data retention of 40 years. these memory devices operate with a power supply down to 1.8 v for the M34C02-r. these memory devices are compatible with the i 2 c memory standard. this is a two wire serial interface that uses a bi-directional data bus and serial clock. the memory carries a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition to access the memory area and a second device type identifier code (0110) to access the protection register. these codes are used together with three chip enable inputs (e2, e1, e0) so that up to eight 2 kbit devices may be attached to the i2c bus and selected individually. the memory behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and rw bit (as described in table 3), terminated by an acknowledge bit. when writing data to the memory, the memory inserts an acknowledge bit during the 9 th bit time, following the bus masters 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the internal reset is held active until the v cc voltage has reached the por threshold value, and all operations are disabled C the device will not respond to any command. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device figure 2. dip, so and tssop connections note: 1. see the pages after page 14 for package dimensions, and how to identify pin-1. sda v ss scl wc e1 e0 v cc e2 ai01932b M34C02 1 2 3 4 8 7 6 5 table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality document s. 2. ipc/jedec j-std-020a. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter value unit t a ambient operating temperature C40 to 85 c t stg storage temperature C65 to 150 c t lead maximum tlead lead temperature during soldering psdip8: 10 sec so8 2 : 20 sec tssop8 2 : 20 sec 260 235 235 c v io input or output range C0.6 to 6.5 v v cc supply voltage C0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 3 4000 v
3/20 M34C02 will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. signal description serial clock (scl) the scl input pin is used to strobe all data in and out of the memory. in applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the scl line to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchronization is not employed, and so the pull- up resistor is not necessary, provided that the master has a push-pull (rather than open drain) output. serial data (sda) the sda pin is bi-directional, and is used to transfer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a pull up resistor must be connected from the sda bus to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). chip enable (e2, e1, e0) these chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs may be driven dynamically or tied to v cc or v ss to establish the device select code. write control (wc ) a hardware write control (wc , pin 7) is provided for protecting the contents of the whole memory from erroneous erase/write cycles. the write control signal is used to enable (wc =v il ) or disable (wc =v ih ) write instructions to the entire memory area or to the protection register. when wc is tied to v ss or left unconnected, the write protection of the first half of the memory is determined by the status of the protection register. device operation the memory device supports the i 2 c protocol. this is summarized in figure 4. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the master, and the other as the slave. a data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. the memory device is always a slave device in all communication. start condition start is identified by a high to low transition of the sda line while the clock, scl, is stable in the high state. a start condition must precede any data transfer command. the memory device continuously monitors (except during a programming cycle) the sda and scl lines for a start condition, and will not respond unless one is given. stop condition stop is identified by a low to high transition of the sda line while the clock scl is stable in the high state. a stop condition terminates communication between the memory device and the bus master. a stop condition at the end of a read command, provided that it is followed by a noack, forces the memory device into its standby figure 3. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k w ) 10 1000 fc = 400khz fc = 100khz
M34C02 4/20 state. a stop condition at the end of a write command triggers the internal eeprom write cycle. acknowledge bit (ack) an acknowledge signal is used to indicate a successful byte transfer. the bus transmitter, whether it be master or slave, releases the sda bus after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls the sda bus low to acknowledge the receipt of the eight data bits. data input during data input, the memory device samples the sda bus signal on the rising edge of the clock, scl. for correct device operation, the sda signal must be stable during the clock low-to-high transition, and the data must change only when the scl line is low. figure 4. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition table 3. device select code 1 note: 1. the most significant bit (b7) is sent first. device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 e2 e1 e0 rw protection register select code 0 1 1 0 e2 e1 e0 rw
5/20 M34C02 memory addressing to start communication between the bus master and the slave memory, the master must initiate a start condition. following this, the master sends the 8-bit byte, shown in table 3, on the sda bus line (most significant bit first). this consists of the 7-bit device select code, and the 1-bit read/write designator (rw ). the device select code is further subdivided into: a 4-bit device type identifier, and a 3-bit chip enable address (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. to address the protection register, it is 0110b. if all three chip enable inputs are connected, up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on its chip enable inputs. when the device select code is received on the sda bus, the memory only responds if the chip select code is the same as the pattern applied to its chip enable pins. the 8 th bit is the read or write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding memory gives an acknowledgment on the sda bus during the 9 th bit time. if the memory does not match the device select code, it will deselect itself from the bus, and go into stand- by mode. write operations following a start condition the master sends a device select code with the rw bit set to 0, as shown in table 4. the memory acknowledges this, and waits for an address byte. the memory responds to the address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if the wc input pin is taken high. byte write in the byte write mode, after the device select code and the address byte, the master sends one data byte. if the addressed location is in a write protected area, the memory replies with a noack, and the location is not modified. if, instead, the addressed location is not in a write protected area, the memory replies with an ack. the master terminates the transfer by generating a stop condition. page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is the most significant memory address bits (b7-b4) are the same. if more bytes are sent than will fit up to the end of the row, a condition known as roll-over occurs. data starts to become overwritten (in a way not formally specified in this data sheet). the master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the wc pin is low. if the wc pin is high, the contents of the addressed memory location are not modified. after each byte is transferred, the internal byte address counter (the 4 least significant bits only) is incremented. the transfer is terminated by the master generating a stop condition. when the master generates a stop condition immediately after the ack bit (in the 10 th bit time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time does not trigger the internal write cycle. during the internal write cycle, the sda input is disabled internally, and the device does not respond to any requests. minimizing system delays by polling on ack during the internal write cycle, the memory disconnects itself from the bus, and copies the table 4. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 3 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0
M34C02 6/20 figure 5. how to set the write protection figure 6. write mode sequences in the non write-protected area default eeprom memory area state before write access to the protect register ai01936c standard array ffh standard array 80h 7fh 00h standard array ffh write protected array 80h 7fh 00h state of the eeprom memory area after write access to the protect register memory area stop start byte write dev sel byte addr data in start page write dev sel byte addr data in 1 data in 2 ai01941 stop data in n ack ack ack r/w ack ack ack r/w ack ack data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 9, but the typical time is shorter. to make use of this, an ack polling sequence can be used by the master. the sequence, as shown in figure 7, is: C initial condition: a write is in progress. C step 1: the master issues a start condition followed by a device select code (the first byte of the new instruction). C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the master goes back to step 1. if the memory has terminated the internal write cycle, it responds with an ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during step 1).
7/20 M34C02 figure 7. write cycle polling flowchart using ack figure 8. setting the write protection register (wc = 0) write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation start sda line ai01935 ack word address value don't care ack data value don't care stop ack control byte bus activity master bus activity
M34C02 8/20 for any other write command, the wc input needs to be held at v ss . address and data bytes must be sent with this command, but their values are all ignored, and are treated as dont care. once the protection register has been written, the write protection of the first 128 bytes of the memory is enabled, and it is not possible to unprotect these 128 bytes, even if the device is powered off and on, and regardless the state of the wc input. when the protection register has been written, the M34C02 no longer responds to the device type identifier 0110b in either read or write mode. setting the protection, using the protection register the M34C02 has a software write-protection function, using the protecton register, that allows the bottom half of the memory area (addresses 00h to 7fh) to be permanently write protected. the write protection feature is activated by writing once to the protection register (with the wc input held at v ss ). the protection register is accessed with the device select code set to 0110b (as shown in table 3), and the e2-e1-e0 bits set according to the states being applied to the e2-e1-e0 pins. as figure 9. read mode sequences note: 1. the seven most significant bits of the device select code of a random read (in the 1 st and 3 rd bytes) must be identical. start dev sel * byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
9/20 M34C02 read operations read operations are performed independently of the state of the wc pin. random address read a dummy write is performed to load the address into the address counter, as shown in figure 9. then, without sending a stop condition, the master sends another start condition, and repeats the device select code, with the rw bit set to 1. the memory acknowledges this, and outputs the contents of the addressed byte. the master must not acknowledge the byte output, and terminates the transfer with a stop condition. current address read the device has an internal address counter which is incremented each time a byte is read. for the current address read mode, following a start condition, the master sends a device select code with the rw bit set to 1. the memory acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the master terminates the transfer with a stop condition, as shown in figure 9, without acknowledging the byte output. sequential read this mode can be initiated with either a current address read or a random address read. the master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. to terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a stop condition. the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter rolls-over and the memory continues to output data from address 00h (at the start of the memory block). acknowledge in read mode in all read modes, the memory waits, after each byte read, for an acknowledgment during the 9 th bit time. if the master does not pull the sda line low during this time, the memory terminates the data transfer and switches to its standby state. use within a dram dimm in the application, the M34C02 is soldered directly in the printed circuit module. the 3 chip enable inputs (pins 1, 2 and 3) are connected to pins 165, 166 and 167, respectively, of the 168-pin dram dimm module. they are wired at v cc or v ss through the dimm socket (see table 5). the scl and sda lines (pins 6 and 5) are connected respectively to pins 83 and 82 of the memory module. the pull-up resistors needed for normal behavior of the i 2 c bus are connected on the i 2 c bus of the mother-board (as shown in figure 10). the write control input of the M34C02 (wc on pin 7) can be left unconnected. however, connecting it to v ss is recommended, to maintain full read and write access to the top half of the memory. programming the M34C02 when the M34C02 is delivered, full read and write access is given to the whole memory array. it is recommended that the first step is to use the test equipment to write the module information (such as its access speed, its size, its organization) to the first half of the memory, starting from the first memory location. when the data has been validated, the test equipment can send a write command to the protection register, using the device select code 01100000b followed by an address and data byte (made up of dont care values) as shown in figure 8. the first 128 bytes of the memory area are then write-protected, and the M34C02 will no longer respond to the specific device select code 0110000xb. it is not possible to reverse this sequence. table 5. 168 pin dram dimm connections dimm position e2 (pin 167) e1 (pin 166) e0 (pin 165) 0 v ss v ss v ss 1 v ss v ss v cc 2 v ss v cc v ss 3 v ss v cc v cc 4 v cc v ss v ss 5 v cc v ss v cc 6 v cc v cc v ss 7 v cc v cc v cc
M34C02 10/20 figure 10. serial presence detect block diagram note: 1. e0, e1 and e2 are wired at each dimm socket in a binary sequence for a maximum of 8 devices. 2. common clock and common data are shared across all the devices. 3. pull-up resistors are required on all sda and scl bus lines (typically 4.7 k w ) because these lines are open drain when used as outputs. r = 4.7k w ai01937 dimm position 7 sda scl e0 e1 e2 v cc dimm position 6 sda scl e0 e1 e2 dimm position 5 sda scl e0 e1 e2 dimm position 4 sda scl e0 e1 e2 dimm position 3 sda scl e0 e1 e2 dimm position 2 sda scl e0 e1 e2 v cc dimm position 1 sda scl e0 e1 e2 dimm position 0 sda scl e0 e1 e2 v ss v ss v ss v cc v ss v ss v cc v cc v ss v cc v cc v ss v ss v cc scl line sda line from the motherboard i 2 c master controller
11/20 M34C02 table 6. dc characteristics (t a = C40 to 85 c; v cc = 2.5 to 5.5 v, 2.2 to 5.5 v or 1.8 to 5.5 v) symbol parameter test condition min. max. unit i li input leakage current scl, sda v in = v ss or v cc 2 a i lo output leakage current 0 v v out v cc, sda in hi-z 2 a i cc supply current -w or -l series v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma -w or -l series v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma -l series v cc =2.2v, f c =400khz (rise/fall time < 30ns) 1ma -r series v cc =1.8v, f c =100khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current all devices v in = v ss or v cc , v cc = 5 v 1a all devices v in = v ss or v cc , v cc = 2.5 v 0.5 a -l or -r series v in = v ss or v cc , v cc = 2.2 v 0.5 a -r series v in = v ss or v cc , v cc = 1.8 v 0.5 a v il input low voltage scl, sda C 0.3 0.3v cc v e0, e1, e2 C 0.3 0.3v cc v wc C 0.3 0.5 v v ih input high voltage scl, sda 0.7v cc v cc +1 v e0, e1, e2 0.7v cc v cc +1 v wc 0.7v cc v cc +1 v v ol output low voltage all devices i ol = 3 ma, v cc = 5 v 0.4 v all devices i ol = 2.1 ma, v cc = 2.5 v 0.4 v -l or -r series i ol = 2.1 ma, v cc = 2.2 v 0.4 v -r series i ol = 0.15 ma, v cc = 1.8 v 0.2 v table 7. ac measurement conditions input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc figure 11. ac testing input output waveforms ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc
M34C02 12/20 table 8. input parameters 1 (t a = 25 c, f = 400 khz) note: 1. sampled only, not 100% tested. table 9. ac characteristics note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. symbol parameter test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance v in < 0.5 v 5 20 k w z wch wc input impedance v in > 0.7v cc 500 k w t ns low pass filter input time constant (scl and sda) 100 500 ns symbol alt. parameter M34C02-w M34C02-l M34C02-r unit v cc =2.5 to 5.5v t a = C40 to 85c v cc =2.2 to 5.5v t a = C40 to 85c v cc =1.8 to 5.5v t a = C0 to 70c min max min max min max t ch1ch2 t r clock rise time 300 300 1000 ns t cl1cl2 t f clock fall time 300 300 300 ns t dh1dh2 2 t r sda rise time 20 300 20 300 20 1000 ns t dl1dl2 2 t f sda fall time 20 300 20 300 20 300 ns t chdx 1 t su:sta clock high to input transition 600 600 4700 ns t chcl t high clock pulse width high 600 600 4000 ns t dlcl t hd:sta input low to clock low (start) 600 600 4000 ns t cldx t hd:dat clock low to input transition 0 0 0 s t clch t low clock pulse width low 1.3 1.3 4.7 s t dxcx t su:dat input transition to clock transition 100 100 250 ns t chdh t su:sto clock high to input high (stop) 600 600 4000 ns t dhdl t buf input high to input low (bus free) 1.3 1.3 4.7 s t clqv 3 t aa clock low to data out valid 200 900 200 900 200 3500 ns t clqx t dh data out hold time after clock low 200 200 200 ns f c f scl clock frequency 400 400 100 khz t w t wr write time 10 10 10 ms
13/20 M34C02 figure 12. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
M34C02 14/20 table 10. ordering information scheme note: 1. package-type available only on request. example: M34C02 Cw mn 6 t operating voltage option w 2.5 v to 5.5 v t tape and reel packing l 2.2 v to 5.5 v r 1.8 v to 5.5 v package temperature range bn 1 psdip8 (0.25 mm frame) 6 C40 c to 85 c mn so8 (150 mil width) 1 C0 c to 70 c dw tssop8 (169 mil width) ds tssop8 (3x3mm2 body size, msop8) the notation used for the device number is as shown in table 10. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. ordering information devices are shipped from the factory with the memory content set at all 1s (ffh), and the protection register set at all 0s (00h).
15/20 M34C02 pdip8 C 8 pin plastic dip, 0.25mm lead frame, package outline note: 1. drawing is not to scale. pdip8 C 8 pin plastic dip, 0.25mm lead frame, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 C C 0.100 C C ea 7.62 C C 0.300 C C eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
M34C02 16/20 so8 narrow C 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. so8 narrow C 8 lead plastic small outline, 150 mils body width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 a 1 h h x 45?
17/20 M34C02 tssop8 C 8 lead thin shrink small outline, package outline note: 1. drawing is not to scale. tssop8 C 8 lead thin shrink small outline, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 a 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1
M34C02 18/20 tssop8 3x3mm2 C 8 lead thin shrink small outline, 3x3mm2 body size, package outline note: 1. drawing is not to scale. tssop8 3x3mm2 C 8 lead thin shrink small outline, 3x3mm2 body size, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.100 0.0433 a1 0.050 0.150 0.0020 0.0059 a2 0.850 0.750 0.950 0.0335 0.0295 0.0374 b 0.250 0.400 0.0098 0.0157 c 0.130 0.230 0.0051 0.0091 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 4.900 4.650 5.150 0.1929 0.1831 0.2028 e1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C cp 0.100 0.0039 l 0.550 0.400 0.700 0.0217 0.0157 0.0276 l1 0.950 0.0374 a 0 6 0 6 tssop8bm 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1
19/20 M34C02 table 11. revision history date rev. description of revision 27-dec-1999 2.0 adjustments to the formatting. 0 to 70c temperature range removed from dc and ac tables. no change to description of device, or parameters 07-dec-2000 2.1 new definition of lead soldering temperature absolute rating for certain packages 13-mar-2001 2.2 -r voltage range added 18-jul-2002 2.3 tssop8 (3x3mm2 body size) package (msop8) added
M34C02 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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